0.3-1.5 V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier.
Toshikazu SuzukiYoshinobu YamagamiIchiro HatanakaAkinori ShibayamaHironori AkamatsuHiroyuki YamauchiPublished in: IEICE Trans. Electron. (2005)