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A sub-0.5-V operating embedded SRAM featuring a multi-bit-error-immune hidden-ECC scheme.
Toshikazu Suzuki
Yoshinobu Yamagami
Ichiro Hatanaka
Akinori Shibayama
Hironori Akamatsu
Hiroyuki Yamauchi
Published in:
IEEE J. Solid State Circuits (2006)
Keyphrases
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bit errors
error correction
error detection
error concealment
video transmission
image sequences
data transmission
entropy coding