Shuhei Iwade

Publication Activity (10 Years)

Years Active: 1994-2016
Publications (10 Years): 2

Top Topics

Motion Estimation Algorithm

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Masahiro Hiramori, Ryota Bandou, Shuhei Iwade, Hiroshi Makino, Tsutomu Yoshimura, Yoshio Matsuda
A study on fast motion estimation algorithm. GCCE (2016)
Ryota Bnadou, Masahiro Hiramori, Shuhei Iwade, Hiroshi Makino, Tutomu Yoshimura, Yoshio Matsuda
A study on motion estimation algorithm for moving pictures. GCCE (2016)
Shunji Nakata, Hiroshi Makino, Junpei Hosokawa, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda
Energy Efficient Stepwise Charging of a Capacitor Using a DC-DC Converter With Consecutive Changes of its Duty Ratio. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2014)
Tsutomu Yoshimura, Shuhei Iwade, Hiroshi Makino, Yoshio Matsuda
Analysis of Pull-in Range Limit by Charge Pump Mismatch in a Linear Phase-Locked Loop. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2013)
Hiroshi Makino, Shunji Nakata, Hirotsugu Suzuki, Shin'ichiro Mutoh, Masayuki Miyama, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda
Utilising the normal distribution of the write noise margin to easily predict the SRAM write yield. IET Circuits Devices Syst. 6 (4) (2012)
Hiroshi Makino, Shunji Nakata, Hirotsugu Suzuki, Shin'ichiro Mutoh, Masayuki Miyama, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda
Reexamination of SRAM Cell Write Margin Definitions in View of Predicting the Distribution. IEEE Trans. Circuits Syst. II Express Briefs (4) (2011)
Koji Nii, Yasumasa Tsukamoto, Tomoaki Yoshizawa, Susumu Imaoka, Yoshinobu Yamagami, Toshikazu Suzuki, Akinori Shibayama, Hiroshi Makino, Shuhei Iwade
A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications. IEEE J. Solid State Circuits 39 (4) (2004)
Hidehiro Takata, Tetsuya Watanabe, Tetsuo Nakajima, Takashi Takagaki, Hisakazu Sato, Atsushi Mohri, Akira Yamada, Toshiki Kanamoto, Yoshio Matsuda, Shuhei Iwade, Yasutaka Horiba
The D30V/MPEG multimedia processor. IEEE Micro 19 (4) (1999)
Koji Nii, Hideshi Maeno, Tokuya Osawa, Shuhei Iwade, Shinpei Kayano, Hiroshi Shibata
A novel memory cell for multiport RAM on 0.5 μm CMOS Sea-of-Gates. IEEE J. Solid State Circuits 30 (3) (1995)
Yoshiki Tsujihashi, Hisashi Matsumoto, Hidekatsu Nishimaki, Atsushi Miyanishi, Hiroomi Nakao, Osamu Kitada, Shuhei Iwade, Shinpei Kayano, Masayoshi Sakao
A high-density data-path generator with stretchable cells. IEEE J. Solid State Circuits 29 (1) (1994)