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A novel memory cell for multiport RAM on 0.5 μm CMOS Sea-of-Gates.
Koji Nii
Hideshi Maeno
Tokuya Osawa
Shuhei Iwade
Shinpei Kayano
Hiroshi Shibata
Published in:
IEEE J. Solid State Circuits (1995)
Keyphrases
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random access memory
low voltage
design considerations
main memory
flash memory
high speed
power consumption
memory requirements
computing power
memory space
memory access
memory usage
analog to digital converter
data sets
memory management
query processing
computational complexity