A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues.

Satoshi Ishikura Marefusa Kurumada Toshio Terano Yoshinobu Yamagami Naoki Kotani Katsuji Satomi Koji Nii Makoto Yabuuchi Yasumasa Tsukamoto Shigeki Ohbayashi Toshiyuki Oashi Hiroshi Makino Hirofumi Shinohara Hironori Akamatsu

Published in: IEEE J. Solid State Circuits (2008)

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