Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors.
Shota MatsunoMasashi TawadaMasao YanagisawaShinji KimuraNozomu TogawaTadahiko SugibayashiPublished in: ASICON (2013)
Keyphrases
- memory subsystem
- multithreading
- main memory
- memory access
- processor core
- memory hierarchy
- ibm zenterprise
- instruction set
- data storage
- parallel computing
- mobile devices
- cache conscious
- data access
- memory bandwidth
- speculative execution
- secondary storage
- computational power
- mobile phone
- database management systems
- flash memory
- memory management
- shared memory
- dynamic random access memory
- data structure
- random access
- index structure
- parallel algorithm
- embedded processors
- parallel processing
- cache misses
- computing environments
- mobile users
- computing power