Masashi Tawada

Publication Activity (10 Years)

Years Active: 2011-2024
Publications (10 Years): 28

Top Topics

Hamming Distance

Vehicle Routing

Code Generation

Subgraph Isomorphism

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

IEEE Trans. Computers

Publications

Siya Bao, Masashi Tawada, Shu Tanaka, Nozomu Togawa
An Ising-Machine-Based Solver of Vehicle Routing Problem With Balanced Pick-Up. IEEE Trans. Consumer Electron. 70 (1) (2024)
Yui Tsuyumine, Kenichi Masuda, Takeshi Hachikawa, Tsuyoshi Haga, Yuta Yachi, Tatsuhiko Shirai, Masashi Tawada, Nozomu Togawa
Optimization of Practical Time-Dependent Vehicle Routing Problem by Ising Machines. ICCE (2024)
Yuta Yachi, Masashi Tawada, Nozomu Togawa
An Efficient Combined Bit-Width Reducing Method for Ising Models. IEICE Trans. Inf. Syst. 106 (4) (2023)
Yuta Yachi, Masashi Tawada, Nozomu Togawa
A Bit-Width Reducing Method for Ising Models Guaranteeing the Ground-State Output. SOCC (2023)
Yuta Yachi, Yousuke Mukasa, Masashi Tawada, Nozomu Togawa
Efficient Coefficient Bit-Width Reduction Method for Ising Machines. ICCE (2022)
Daisuke Oku, Masashi Tawada, Shu Tanaka, Nozomu Togawa
How to Reduce the Bit-Width of an Ising Model by Adding Auxiliary Spins. IEEE Trans. Computers 71 (1) (2022)
Tomokazu Yoshimura, Tatsuhiko Shirai, Masashi Tawada, Nozomu Togawa
QUBO Matrix Distorting Method for Consumer Applications. ICCE (2022)
Yuta Atobe, Masashi Tawada, Nozomu Togawa
Hybrid Annealing Method Based on subQUBO Model Extraction With Multiple Solution Instances. IEEE Trans. Computers 71 (10) (2022)
Siya Bao, Masashi Tawada, Shu Tanaka, Nozomu Togawa
An Approach to the Vehicle Routing Problem with Balanced Pick-up Using Ising Machines. VLSI-DAT (2021)
Shota Matsuno, Masashi Tawada, Nozomu Togawa
Reducing Writing Energy Consumption for Non-Volatile Registers Utilizing Frequent Patterns of Sequential Bits on RISC-V Architecture. ICCE (2021)
Siya Bao, Masashi Tawada, Shu Tanaka, Nozomu Togawa
Multi-day Travel Planning Using Ising Machines for Real-world Applications. ITSC (2021)
Natsuhito Yoshimura, Masashi Tawada, Shu Tanaka, Junya Arai, Satoshi Yagi, Hiroyuki Uchiyama, Nozomu Togawa
Mapping Induced Subgraph Isomorphism Problems to Ising Models and Its Evaluations by an Ising Machine. IEICE Trans. Inf. Syst. (4) (2021)
Kento Hasegawa, Ryota Ishikawa, Makoto Nishizawa, Kazushi Kawamura, Masashi Tawada, Nozomu Togawa
FPGA-based Heterogeneous Solver for Three-Dimensional Routing. ASP-DAC (2020)
Masashi Tawada, Shu Tanaka, Nozomu Togawa
A New LDPC Code Decoding Method: Expanding the Scope of Ising Machines. ICCE (2020)
Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
Scalable Stochastic Number Duplicators for Accuracy-flexible Arithmetic Circuit Design. IPSJ Trans. Syst. LSI Des. Methodol. 13 (2020)
Masashi Tawada, Nozomu Togawa
Designing Stochastic Number Generators Sharing a Random Number Source based on the Randomization Function. NEWCAS (2020)
Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
Multi-Resolutional Image Format Using Stochastic Numbers and Its Hardware Implementation. LASCAS (2020)
Natsuhito Yoshimura, Masashi Tawada, Shu Tanaka, Junya Arai, Satoshi Yagi, Hiroyuki Uchiyama, Nozomu Togawa
Efficient Ising Model Mapping for Induced Subgraph Isomorphism Problems Using Ising Machines. ICCE-Berlin (2019)
Yuta Ideguchi, Norifumi Kamiya, Masashi Tawada, Nozomu Togawa
Effectively Partitioned Implementation for Successive-Cancellation Polar Decoder. MWSCAS (2019)
Sho Kanamaru, Daisuke Oku, Masashi Tawada, Shu Tanaka, Masato Hayashi, Masanao Yamaoka, Masao Yanagisawa, Nozomu Togawa
Efficient Ising Model Mapping to Solving Slot Placement Problem. ICCE (2019)
Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
Error Correction System using Stochastic Numbers in Symmetric Channels and Z Channels. ICECS (2019)
Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
Error Correction Coding of Stochastic Numbers Using BER Measurement. IOLTS (2019)
Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
A Relaxed Bit-Write-Reducing and Error-Correcting Code for Non-Volatile Memories. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2018)
Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
An Effective Stochastic Number Duplicator and Its Evaluations Using Composite Arithmetic Circuits. IOLTS (2018)
Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
2n RRR: Improved Stochastic Number Duplicator Based on Bit Re-Arrangement. NGCAS (2018)
Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
Stochastic Number Duplicators Based on Bit Re-Arrangement Using Randomized Bit Streams. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2018)
Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa
Effective write-reduction method for MLC non-volatile memory. ISCAS (2017)
Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
A Bit-Write-Reducing and Error-Correcting Code Generation Method by Clustering ECC Codewords for Non-Volatile Memories. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2016)
Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
Code Generation Limiting Maximum and Minimum Hamming Distances for Non-Volatile Memories. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2015)
Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
Bit-Write-Reducing and Error-Correcting Code Generation by Clustering Error-Correcting Codewords for Non-Volatile Memories. ICCAD (2015)
Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa
A bit-write reduction method based on error-correcting codes for non-volatile memories. ASP-DAC (2015)
Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa
ECC-Based Bit-Write Reduction Code Generation for Non-Volatile Memory. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2015)
Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
A write-reducing and error-correcting code generation method for non-volatile memories. APCCAS (2014)
Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
A High-Speed Trace-Driven Cache Configuration Simulator for Dual-Core Processor L1 Caches. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (6) (2013)
Shota Matsuno, Masashi Tawada, Masao Yanagisawa, Shinji Kimura, Nozomu Togawa, Tadahiko Sugibayashi
Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors. ASICON (2013)
Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
Exact, Fast and Flexible L1 Cache Configuration Simulation for Embedded Systems. Inf. Media Technol. 6 (4) (2011)
Masashi Tawada, Masao Yanagisawa, Nozomu Togawa
Speeding-up exact and fast FIFO-based cache configuration simulation. IEICE Electron. Express 8 (14) (2011)
Masashi Tawada, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa
Exact, Fast and Flexible L1 Cache Configuration Simulation for Embedded Systems. IPSJ Trans. Syst. LSI Des. Methodol. 4 (2011)