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A High-Speed Trace-Driven Cache Configuration Simulator for Dual-Core Processor L1 Caches.
Masashi Tawada
Masao Yanagisawa
Nozomu Togawa
Published in:
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2013)
Keyphrases
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high speed
caching scheme
cache hit ratio
cache misses
prefetching
access latency
memory access
low power
main memory
simulation model
real time
hit rate
hit ratio
cache consistency
primal dual
garbage collection
high speed networks
optimal configuration
gigabit ethernet