Login / Signup

An 8K H.265/HEVC Video Decoder Chip With a New System Pipeline Design.

Dajiang ZhouShihao WangHeming SunJian-Bin ZhouJiayi ZhuYijin ZhaoJinjia ZhouShuping ZhangShinji KimuraTakeshi YoshimuraSatoshi Goto
Published in: IEEE J. Solid State Circuits (2017)
Keyphrases
  • design process
  • single chip
  • image processing
  • video sequences
  • high speed
  • video codec
  • video decoder
  • memory subsystem