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Low Power Test Compression Technique for Designs with Multiple Scan Chain.
Youhua Shi
Nozomu Togawa
Masao Yanagisawa
Tatsuo Ohtsuki
Shinji Kimura
Published in:
Asian Test Symposium (2005)
Keyphrases
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low power
power consumption
low cost
high speed
single chip
high power
low power consumption
wireless transmission
nm technology
compression algorithm
image sensor
vlsi architecture
image processing
image compression
digital signal processing
gate array