14.7 A 4Gpixel/s 8/10b H.265/HEVC video decoder chip for 8K Ultra HD applications.
Dajiang ZhouShihao WangHeming SunJian-Bin ZhouJiayi ZhuYijin ZhaoJinjia ZhouShuping ZhangShinji KimuraTakeshi YoshimuraSatoshi GotoPublished in: ISSCC (2016)
Keyphrases
- video codec
- video decoder
- memory subsystem
- high speed
- video coding
- video quality
- rate distortion
- low power consumption
- transform domain
- low cost
- video compression
- inter frame
- motion compensation
- motion compensated
- low bit rate
- frame rate
- bit rate
- bitstream
- low power
- macroblock
- motion vectors
- motion estimation
- single chip
- video conferencing
- real time
- video frames
- computational complexity