Taeko Matsunaga

Publication Activity (10 Years)

Years Active: 2007-2013
Publications (10 Years): 0

Top Topics

Pruning Algorithm

Functional Programs

Tree Structures

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

Publications

Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
An Exact Approach for GPC-Based Compressor Tree Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2013)
Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
Multi-Operand Adder Synthesis Targeting FPGAs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2011)
Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs. ISLPED (2011)
Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
Multi-operand adder synthesis on FPGAs using generalized parallel counters. ASP-DAC (2010)
Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
Framework for Parallel Prefix Adder Synthesis Considering Switching Activities. IPSJ Trans. Syst. LSI Des. Methodol. 2 (2009)
Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
Synthesis of parallel prefix adders considering switching activities. ICCD (2008)
Taeko Matsunaga, Yusuke Matsunaga
Area minimization algorithm for parallel prefix adders under bitwise delay constraints. ACM Great Lakes Symposium on VLSI (2007)
Taeko Matsunaga, Yusuke Matsunaga
Timing-Constrained Area Minimization Algorithm for Parallel Prefix Adders. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2007)