Multi-operand adder synthesis on FPGAs using generalized parallel counters.
Taeko MatsunagaShinji KimuraYusuke MatsunagaPublished in: ASP-DAC (2010)
Keyphrases
- parallel architectures
- parallel processing
- information retrieval
- program synthesis
- massively parallel
- shared memory
- parallel implementation
- website
- embedded systems
- image processing
- computer architecture
- field programmable gate array
- parallel computation
- distributed memory
- parallel programming
- computer vision
- data mining
- distributed memory machines