A Variable-Clock-Cycle-Path VLSI Design of Binary Arithmetic Decoder for H.265/HEVC.
Jinjia ZhouDajiang ZhouShuping ZhangShinji KimuraSatoshi GotoPublished in: IEEE Trans. Circuits Syst. Video Technol. (2018)
Keyphrases
- vlsi design
- video codec
- low complexity
- design methodology
- power consumption
- video coding standard
- high efficiency video coding
- multiview video coding
- video coding
- rate distortion
- high speed
- video compression
- low bit rate
- neural network
- motion estimation
- relational databases
- inter frame
- distributed video coding
- error concealment
- database applications
- bit rate
- computational complexity