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Low-Power Motion Estimation Processor with 3D Stacked Memory.
Shuping Zhang
Jinjia Zhou
Dajiang Zhou
Shinji Kimura
Satoshi Goto
Published in:
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2015)
Keyphrases
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low power
motion estimation
high speed
single chip
gate array
power consumption
low cost
power dissipation
low complexity
vlsi architecture
high power
digital signal processing
image sequences
video sequences
optical flow
logic circuits
vlsi circuits
video coding
motion compensated
wireless transmission
inter frame
motion compensation
main memory
motion vectors
super resolution
computational complexity
power reduction
video compression
low power consumption
parallel processing
cmos technology
computer vision
signal processor
nm technology
real time
multithreading
frame rate
mixed signal
signal processing