A Reconfigurable Processor Based on ALU Array Architecture with Limitation on the Interconnection.
Makoto OkadaTatsuo HiramatsuHiroshi NakajimaMakoto OzoneKatsunori HiraseShinji KimuraPublished in: IPDPS (2005)
Keyphrases
- systolic array
- parallel architecture
- reconfigurable architecture
- data flow
- instruction set
- computation intensive
- digital signal
- functional units
- floating point
- general purpose processors
- hardware implementation
- management system
- low cost
- software architecture
- multi processor
- heterogeneous computing
- memory management
- industry standard
- processing elements
- reconfigurable hardware
- parallel processing
- real time
- single chip
- level parallelism
- design considerations
- xilinx virtex
- hardware and software
- high speed
- general purpose