Mehran Goli

Publication Activity (10 Years)

Years Active: 2014-2023
Publications (10 Years): 36

Top Topics

Formal Verification

Information Flow

Regression Analysis

Automated Design

Top Venues

Publications

Sajjad Parvin, Mehran Goli, Frank Sill Torres, Rolf Drechsler
FELOPi: A Framework for Simulation and Evaluation of Post-Layout File Against Optical Probing. DATE (2023)
Weiyan Zhang, Mehran Goli, Muhammad Hassan, Rolf Drechsler
Efficient ML-Based Performance Estimation Approach Across Different Microarchitectures for RISC-V Processors. DSD (2023)
Ece Nur Demirhan Coskun, Muhammad Hassan, Mehran Goli, Rolf Drechsler
VAST: Validation of VP-based Heterogeneous Systems against Availability Security Properties using Static Information Flow Tracking. ISQED (2023)
Christopher A. Metz, Mehran Goli, Rolf Drechsler
Fast and Accurate: Machine Learning Techniques for Performance Estimation of CNNs for GPGPUs. IPDPS Workshops (2023)
Sajjad Parvin, Mehran Goli, Frank Sill Torres, Rolf Drechsler
Trojan-D2: Post-Layout Design and Detection of Stealthy Hardware Trojans - A RISC-V Case Study. ASP-DAC (2023)
Rune Krauss, Mehran Goli, Rolf Drechsler
Efficient Binary Decision Diagram Manipulation by Reducing the Number of Intermediate Nodes. DDECS (2023)
Lennart Weingarten, Alireza Mahzoon, Mehran Goli, Rolf Drechsler
Polynomial Formal Verification of a Processor: A RISC-V Case Study. ISQED (2023)
Sajjad Parvin, Mehran Goli, Thilo Krachenfels, Shahin Tajik, Jean-Pierre Seifert, Frank Sill Torres, Rolf Drechsler
LAT-UP: Exposing Layout-Level Analog Hardware Trojans Using Contactless Optical Probing. ISVLSI (2023)
Rune Krauss, Mehran Goli, Rolf Drechsler
EDDY: A Multi-Core BDD Package with Dynamic Memory Management and Reduced Fragmentation. ASP-DAC (2023)
Weiyan Zhang, Mehran Goli, Rolf Drechsler
Early Performance Estimation of Embedded Software on RISC-V Processor using Linear Regression. DDECS (2022)
Christopher A. Metz, Mehran Goli, Rolf Drechsler
Towards Neural Hardware Search: Power Estimation of CNNs for GPGPUs with Dynamic Frequency Scaling. MLCAD (2022)
Christopher A. Metz, Mehran Goli, Rolf Drechsler
ML-based Power Estimation of Convolutional Neural Networks on GPGPUs. DDECS (2022)
Rolf Drechsler, Alireza Mahzoon, Mehran Goli
Towards Polynomial Formal Verification of Complex Arithmetic Circuits. DDECS (2022)
Mehran Goli, Rolf Drechsler
Simulation-based Verification of SystemC-based VPs at the ESL. CoRR (2022)
Mehran Goli, Rolf Drechsler
Through the Looking Glass: Automated Design Understanding of SystemC-Based VPs at the ESL. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (4) (2022)
Weiyan Zhang, Mehran Goli, Alireza Mahzoon, Rolf Drechsler
ANN-based Performance Estimation of Embedded Software for RISC-V Processors. RSP (2022)
Mehran Goli, Rolf Drechsler
Simulation-based Verification of SystemC-based VPs at the ESL. MBMV (2022)
Christopher A. Metz, Mehran Goli, Rolf Drechsler
Pick the Right Edge Device: Towards Power and Performance Estimation of CUDA-based CNNs on GPGPUs. CoRR (2021)
Mehran Goli, Alireza Mahzoon, Rolf Drechsler
Automated Debugging-Aware Visualization Technique for SystemC HLS Designs. DSD (2021)
Mehran Goli, Rolf Drechsler
ATLaS: Automatic Detection of Timing-based Information Leakage Flows for SystemC HLS Designs. ASP-DAC (2021)
Mehran Goli, Rolf Drechsler
Early Validation of SoCs Security Architecture Against Timing Flows Using SystemC-based VPs. ICCAD (2021)
Mehran Goli, Rolf Drechsler
VIP-VP: Early Validation of SoCs Information Flow Policies using SystemC-based Virtual Prototypes. FDL (2021)
Christopher A. Metz, Mehran Goli, Rolf Drechsler
Early power estimation of CUDA-based CNNs on GPGPUs: work-in-progress. CODES+ISSS (2021)
Mehran Goli, Jannis Stoppe, Rolf Drechsler
Automated Nonintrusive Analysis of Electronic System Level Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (2) (2020)
David Lemma, Mehran Goli, Daniel Große, Rolf Drechsler
Towards Generation of a Programmable Power Management Unit at the Electronic System Level. DDECS (2020)
Mehran Goli, Rolf Drechsler
PREASC: Automatic Portion Resilience Evaluation for Approximating SystemC-based Designs Using Regression Analysis Techniques. ACM Trans. Design Autom. Electr. Syst. 25 (5) (2020)
Mehran Goli, Alireza Mahzoon, Rolf Drechsler
ASCHyRO: Automatic Fault Localization of SystemC HLS Designs Using a Hybrid Accurate Rank Ordering Technique. ICCD (2020)
Mehran Goli, Rolf Drechsler
Automated Design Understanding of SystemC-Based Virtual Prototypes: Data Extraction, Analysis and Visualization. ISVLSI (2020)
Mehran Goli, Rolf Drechsler
Scalable Simulation-Based Verification of SystemC-Based Virtual Prototypes. DSD (2019)
Mehran Goli, Muhammad Hassan, Daniel Große, Rolf Drechsler
Security validation of VP-based SoCs using dynamic information flow tracking. it Inf. Technol. 61 (1) (2019)
Mehran Goli, Muhammad Hassan, Daniel Große, Rolf Drechsler
Automated Analysis of Virtual Prototypes at Electronic System Level. ACM Great Lakes Symposium on VLSI (2019)
Mehran Goli, Jannis Stoppe, Rolf Drechsler
Resilience Evaluation for Approximating SystemC Designs Using Machine Learning Techniques. RSP (2018)
David Lemma, Mehran Goli, Daniel Große, Rolf Drechsler
. NORCAS (2018)
Mehran Goli, Jannis Stoppe, Rolf Drechsler
Automatic Protocol Compliance Checking of SystemC TLM-2.0 Simulation Behavior Using Timed Automata. ICCD (2017)
Mehran Goli, Jannis Stoppe, Rolf Drechsler
Automatic equivalence checking for SystemC-TLM 2.0 models against their formal specifications. DATE (2017)
Mehran Goli, Jannis Stoppe, Rolf Drechsler
AIBA: An Automated Intra-cycle Behavioral Analysis for SystemC-based design exploration. ICCD (2016)
Mehran Goli, Amin Ghasemazar, Zainalabedin Navabi
Application-specific power-aware mapping for reconfigurable NoC architectures. DTIS (2015)
Amin Ghasemazar, Mehran Goli, Ali Afzali-Kusha
Embedded Complex Floating Point Hardware Accelerator. VLSI Design (2014)