Nooshin Nosrati

Publication Activity (10 Years)

Years Active: 2019-2024
Publications (10 Years): 14

Top Topics

Error Detection

Embedded Processors

Top Venues

Publications

Nooshin Nosrati, Zainalabedin Navabi
Analysis and Enhancement of Resilience for LSTM Accelerators Using Residue-Based CEDs. IEEE Access 12 (2024)
Nooshin Nosrati, Zainalabedin Navabi
A Low-cost Residue-based Scheme for Error-resiliency of RNN Accelerators. DDECS (2023)
Ebrahim Nouri, Nooshin Nosrati, Hanieh Totonchi Asl, Mozhgan Rezaie Manavand, Zainalabedin Navabi
Multi-Level Fault Injection Methodology Using UVM-SystemC. EWDTS (2023)
Katayoon Basharkhah, Raheleh Sadat Mirhashemi, Nooshin Nosrati, Mohammad-Javad Zare, Zainalabedin Navabi
Learning Electrical Behavior of Core Interconnects for System-Level Crosstalk Prediction. ETS (2023)
Nooshin Nosrati, Seyedeh Maryam Ghasemi, Mahboobe Sadeghipour Roodsari, Zainalabedin Navabi
Concurrent Error Detection for LSTM Accelerators. ETS (2022)
Nooshin Nosrati, Maksim Jenihhin, Zainalabedin Navabi
MLC: A Machine Learning Based Checker For Soft Error Detection In Embedded Processors. IOLTS (2022)
Nooshin Nosrati, Katayoon Basharkhah, Hanieh Totonchi Asl, Zahra Mahdavi, Zainalabedin Navabi
Testing a RISCV-Like Architecture With an HDL-Based Virtual Tester. DTIS (2021)
Saba Yousefzadeh, Katayoon Basharkhah, Nooshin Nosrati, Maryam Rajabalipanah, Seyedeh Maryam Ghasemi, Zainalabedin Navabi
Reconfiguration of Embedded Accelerators by Microprogramming for Intensive Loop Computations. DDECS (2020)
Maryam Rajabalipanah, Seyedeh Maryam Ghasemi, Nooshin Nosrati, Katayoon Basharkhah, Saba Yousefzadeh, Zainalabedin Navabi
Reducing DFT hardware overhead by use of a test microprogram in a microprogrammed hardware accelerator. DFT (2020)
Katayoon Basharkhah, Rezgar Sadeghi, Nooshin Nosrati, Zainalabedin Navabi
ESL, Back-annotating Crosstalk Fault Models into High-level Communication Links. VTS (2020)
Nooshin Nosrati, Katayoon Basharkhah, Rezgar Sadeghi, Zainalabedin Navabi
An ESL Environment for Modeling Electrical Interconnect Faults. ISVLSI (2019)
Rezgar Sadeghi, Nooshin Nosrati, Katayoon Basharkhah, Zainalabedin Navabi
Back-annotation of Interconnect Physical Properties for System-Level Crosstalk Modeling. ETS (2019)
Nooshin Nosrati, Katayoon Basharkhah, Rezgar Sadeghi, Carna Zivkovic, Christoph Grimm, Zainalabedin Navabi
Making System Level Test Possible by a Mixed-mode, Multi-level, Integrated Modeling Environment. EWDTS (2019)
Saba Yousefzadeh, Katayoon Basharkhah, Nooshin Nosrati, Rezgar Sadeghi, Jaan Raik, Maksim Jenihhin, Zainalabedin Navabi
An Accelerator-based Architecture Utilizing an Efficient Memory Link for Modern Computational Requirements. EWDTS (2019)