Reducing DFT hardware overhead by use of a test microprogram in a microprogrammed hardware accelerator.
Maryam RajabalipanahSeyedeh Maryam GhasemiNooshin NosratiKatayoon BasharkhahSaba YousefzadehZainalabedin NavabiPublished in: DFT (2020)
Keyphrases
- low cost
- hardware and software
- real time
- computer systems
- computing systems
- field programmable gate array
- massively parallel
- vlsi implementation
- hardware architecture
- hardware software co design
- computing power
- learning algorithm
- computer architecture
- parallel implementation
- high end
- personal computer
- test data
- control program
- parallel hardware