Optimistic clock adjustment for preventing Better-than-worst-case violations.
Seyedeh Hanieh HashemiReza NamazianZainalabedin NavabiPublished in: VLSI-SoC (2016)
Keyphrases
- worst case
- average case
- upper bound
- error bounds
- high speed
- lower bound
- approximation algorithms
- greedy algorithm
- np hard
- duty cycle
- power consumption
- running times
- computational complexity
- worst case analysis
- constraint violations
- case study
- artificial intelligence
- real time
- worst case scenario
- search algorithm
- bayesian networks
- databases
- data sets