Robert Michael Owens

Publication Activity (10 Years)

Years Active: 1979-2000
Publications (10 Years): 0

Publications

Eric Gayles, Thomas P. Kelliher, Robert Michael Owens, Mary Jane Irwin
The design of the MGAP-2: a micro-grained massively parallel array. IEEE Trans. Very Large Scale Integr. Syst. 8 (6) (2000)
Manjit Borah, Robert Michael Owens, Mary Jane Irwin
A Fast and Simple Steiner Routing Heuristic. Discret. Appl. Math. 90 (1-3) (1999)
Benjamin Bishop, Thomas P. Kelliher, Robert Michael Owens, Mary Jane Irwin
Aggressive Dynamic Execution of Decoded Traces. J. VLSI Signal Process. 22 (1) (1999)
Rita Yu Chen, Robert Michael Owens, Mary Jane Irwin, Raminder Singh Bajwa
Validation of an Architectural Level Power Analysis Technique. DAC (1998)
Benjamin Bishop, Robert Michael Owens, Mary Jane Irwin
Aggressive Dynamic Execution of Multimedia Kernel Traces. IPPS/SPDP (1998)
Robert Michael Owens, Mohan Vishwanath
A Very Efficient Storage Structure for DWT and IDWT Filters. J. VLSI Signal Process. 19 (3) (1998)
Kevin P. Acken, Mary Jane Irwin, Robert Michael Owens
A Parallel ASIC Architecture for Efficient Fractal Image Coding. J. VLSI Signal Process. 19 (2) (1998)
Huzefa Mehta, Robert Michael Owens, Mary Jane Irwin
A Simulation Methodology for Software Energy Evaluation. VLSI Design (1997)
Meng-Fan Chang, Mary Jane Irwin, Robert Michael Owens
Power-Area Trade-Offs in Divided Word Line Memory Arrays. J. Circuits Syst. Comput. 7 (1) (1997)
Heung-Nam Kim, Mary Jane Irwin, Robert Michael Owens
Motion Analysis on the Micro Grained Array Processor. Real Time Imaging 3 (2) (1997)
Patrick Hicks, Matthew Walnock, Robert Michael Owens
Analysis of power consumption in memory hierarchies. ISLPED (1997)
Manjit Borah, Robert Michael Owens, Mary Jane Irwin
A fast algorithm for minimizing the Elmore delay to identified critical sinks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (7) (1997)
Eric Gayles, Kevin P. Acken, Robert Michael Owens, Mary Jane Irwin
A Clocked, Static Circuit Technique for Building Efficient High Frequency Pipelines. Great Lakes Symposium on VLSI (1997)
Huzefa Mehta, Robert Michael Owens, Mary Jane Irwin, Rita Yu Chen, Debashree Ghosh
Techniques for low energy software. ISLPED (1997)
Kevin P. Acken, Eric Gayles, Thomas P. Kelliher, Robert Michael Owens, Mary Jane Irwin
The MGAP Family of Processor Arrays. Great Lakes Symposium on VLSI (1997)
Raminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin
Mixed-autonomy local interconnect for reconfigurable SIMD arrays. HiPC (1997)
Manjit Borah, Robert Michael Owens, Mary Jane Irwin
Transistor sizing for low power CMOS circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (6) (1996)
Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin
Design tradeoffs in high speed multipliers and FIR filters. VLSI Design (1996)
Manjit Borah, Robert Michael Owens, Mary Jane Irwin
Recent Developments in Performance Driven Steiner Routing: An Overview. Great Lakes Symposium on VLSI (1996)
Huzefa Mehta, Robert Michael Owens, Mary Jane Irwin
Some Issues in Gray Code Addressing. Great Lakes Symposium on VLSI (1996)
Huzefa Mehta, Robert Michael Owens, Mary Jane Irwin
Instruction level power profiling. ICASSP (1996)
Kevin P. Acken, Mary Jane Irwin, Robert Michael Owens
Power comparisons for barrel shifters. ISLPED (1996)
Huzefa Mehta, Robert Michael Owens, Mary Jane Irwin
Energy Characterization based on Clustering. DAC (1996)
Chaitali Chakrabarti, Mohan Vishwanath, Robert Michael Owens
Architectures for wavelet transforms: A survey. J. VLSI Signal Process. 14 (2) (1996)
Kevin P. Acken, Heung-Nam Kim, Mary Jane Irwin, Robert Michael Owens
An Architectural Design For Parallel Fractal Compression. ASAP (1996)
Mohan Vishwanath, Robert Michael Owens
A Common Architecture For The DWT and IDWT. ASAP (1996)
Raminder Singh Bajwa, Robert Michael Owens, Thomas P. Kelliher
Simultaneous speech segmentation and phoneme recognition using dynamic programming. ICASSP (1996)
Kevin P. Acken, Mary Jane Irwin, Robert Michael Owens, Amulya K. Garga
Architectural Optimizations For A Floating Point Multiply-Accumulate Unit In A Graphics Pipeline. ASAP (1996)
Manjit Borah, Chetana Nagendra, Mohan Vishwanath, Robert Michael Owens, Mary Jane Irwin
An optimal time multiplication free algorithm for edge detection on a mesh. J. VLSI Signal Process. 13 (1) (1996)
Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin
Digit pipelined arithmetic on fine-grain array processors. J. VLSI Signal Process. 9 (3) (1995)
Robert Michael Owens, Raminder Singh Bajwa, Mary Jane Irwin
Reducing the number of counters needed for integer multiplication. IEEE Symposium on Computer Arithmetic (1995)
Manjit Borah, Robert Michael Owens, Mary Jane Irwin
Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint. ISLPD (1995)
Chaitali Chakrabarti, Mohan Vishwanath, Robert Michael Owens
A survey of architectures for the discrete and continuous wavelet transforms. ICASSP (1995)
Thomas P. Kelliher, Eric Gayles, Robert Michael Owens, Mary Jane Irwin
The MGAP-2: an advanced, massively parallel VLSI signal processor. ICASSP (1995)
Manjit Borah, Robert Michael Owens, Mary Jane Irwin
High-throughput and low-power DSP using clocked-CMOS circuitry. ISLPD (1995)
Manjit Borah, Robert Michael Owens, Mary Jane Irwin
Fast algorithm for performance-oriented Steiner routing. Great Lakes Symposium on VLSI (1995)
Heung-Nam Kim, Mary Jane Irwin, Robert Michael Owens
Motion Estimation Algorithms on Fine Grain Array Processor. ASAP (1995)
Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin
Unifying carry-sum and signed-digital number representations for low power. ISLPD (1995)
Manjit Borah, Mary Jane Irwin, Robert Michael Owens
Minimizing power consumption of static CMOS circuits by transistor sizing and input reordering. VLSI Design (1995)
Raminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin
The MGAP's programming environment and the *C++ language. ASAP (1995)
Huzefa Mehta, Manjit Borah, Robert Michael Owens, Mary Jane Irwin
Accurate Estimation of Combinational Circuit Activity. DAC (1995)
Paul Keltcher, Robert Michael Owens, Mary Jane Irwin
A simulation methodology for evaluating parallel computers. SPDP (1995)
Wen-Lin Yang, Robert Michael Owens, Mary Jane Irwin
FPGA-based synthesis of FSMs through decomposition. Great Lakes Symposium on VLSI (1994)
Manjit Borah, Robert Michael Owens, Mary Jane Irwin
An edge-based heuristic for Steiner routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (12) (1994)
Manjit Borah, Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin
The MGAP: A High Performance, User Programmable, Multifunctional Architecture for DS. HICSS (1) (1994)
Gueesang Lee, Mary Jane Irwin, Robert Michael Owens
Polynomial Time Testability of Circuits Generated by Input Decomposition. IEEE Trans. Computers 43 (2) (1994)
Raminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin
Area Time Trade-Offs in Micro-Grain VLSI Array Architectures. IEEE Trans. Computers 43 (10) (1994)
TingTing Hwang, Robert Michael Owens, Mary Jane Irwin, Kuo-Hua Wang
Logic synthesis for field-programmable gate arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (10) (1994)
Heung-Nam Kim, Mary Jane Irwin, Robert Michael Owens, Chen-Mi Wu
Dynamic Space Warping Algorithms on Fine-Graln Array Processors. IPPS (1994)
Chetana Nagendra, Mary Jane Irwin, Robert Michael Owens
Digit pipelined discrete wavelet transform. ICASSP (2) (1994)
Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin
Power-delay characteristics of CMOS adders. IEEE Trans. Very Large Scale Integr. Syst. 2 (3) (1994)
Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin
Digit systolic algorithms for fine-grain architectures. ASAP (1993)
Wen-Lin Yang, Robert Michael Owens, Mary Jane Irwin
Multi-way FSM decomposition based on interconnect complexity. EURO-DAC (1993)
Chetana Nagendra, Manjit Borah, Mohan Vishwanath, Robert Michael Owens, Mary Jane Irwin
Edge detection using fine-grained parallelism in VLSI. ICASSP (1) (1993)
Chen-Mi Wu, Mohan Vishwanath, Robert Michael Owens, Mary Jane Irwin
A new blocked IIR algorithm. ICASSP (3) (1993)
Robert Michael Owens, Thomas P. Kelliher, Mary Jane Irwin, Mohan Vishwanath, Raminder Singh Bajwa, Wen-Lin Yang
The design and implementation of the Arithmetic Cube II, a VLSI signal processing system. IEEE Trans. Very Large Scale Integr. Syst. 1 (4) (1993)
Raminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin
Image Processing with the MGAP: A Cost Effective Solution. IPPS (1993)
Raminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin
A Massively Parallel, Micro-Grained VLSI Architecture. VLSI Design (1993)
TingTing Hwang, Robert Michael Owens, Mary Jane Irwin
Efficiently computing communication complexity for multilevel logic synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 (5) (1992)
Mohan Vishwanath, Robert Michael Owens, Mary Jane Irwin
Discrete wavelet transforms in VLSI. ASAP (1992)
Soohong Kim, Robert Michael Owens, Mary Jane Irwin
Experiments with a Performance Driven Module Generator. DAC (1992)
Soohong Kim, Robert Michael Owens, Mary Jane Irwin
PERFLEX: a performance driven module generator. EURO-DAC (1992)
Mohan Vishwanath, Robert Michael Owens
lower bound for wavelet transforms in VLSI. ICASSP (1992)
Thomas P. Kelliher, Robert Michael Owens, Mary Jane Irwin, TingTing Hwang
ELM-A Fast Addition Algorithm Discovered by a Program. IEEE Trans. Computers 41 (9) (1992)
Mohan Vishwanath, Robert Michael Owens, Mary Jane Irwin
ECube: An Efficient Architecture for Analyzing Time-Varying Spectra. VLSI Design (1992)
Robert Michael Owens, Mary Jane Irwin, Thomas P. Kelliher, Mohan Vishwanath, Raminder Singh Bajwa
Implementing a family of high performance, micrograined architectures. ASAP (1992)
Mary Jane Irwin, Robert Michael Owens
A micro-grained VLSI signal processor. ICASSP (1992)
Mary Jane Irwin, Robert Michael Owens
A Two-Dimensional, Distributed Logic Architecture. IEEE Trans. Computers 40 (10) (1991)
Poras T. Balsara, Robert Michael Owens, Mary Jane Irwin
Digit Serial Multipliers. J. Parallel Distributed Comput. 11 (2) (1991)
Mohan Vishwanath, Robert Michael Owens, Mary Jane Irwin
The Arithmetic Cube: error analysis and simulation. ASAP (1991)
Mary Jane Irwin, Robert Michael Owens, Thomas P. Kelliher, Kin-Ki Leung, Mohan Vishwanath
The arithmetic cube II: a second generation VLSI DSP processor. ICASSP (1991)
Mary Jane Irwin, Robert Michael Owens
A two-dimensional, distributed logic processor for machine vision. ICASSP (1990)
Chen-Mie Wu, Robert Michael Owens, Mary Jane Irwin
Mapping high-dimension wavefront computations to silicon. ASAP (1990)
Robert Michael Owens, Mary Jane Irwin
Being Stingy with Multipliers. IEEE Trans. Computers 39 (6) (1990)
Barry M. Pangrle, Pao-Po Hou, Robert Michael Owens, Mary Jane Irwin
An integrated, multi-level synthesis system. RSP (1990)
Gueesang Lee, Mary Jane Irwin, Robert Michael Owens
Test generation in circuits constructed by input decomposition. ICCD (1990)
Mary Jane Irwin, Robert Michael Owens
A case for digit serial VLSI signal processors. J. VLSI Signal Process. 1 (4) (1990)
Chen-Mi Wu, Robert Michael Owens, Mary Jane Irwin
Distortion processing in image matching problems. ICASSP (1990)
TingTing Hwang, Robert Michael Owens, Mary Jane Irwin
Logic synthesis for programmable logic devices. ICCD (1990)
TingTing Hwang, Robert Michael Owens, Mary Jane Irwin
Exploiting communication complexity for multilevel logic synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9 (10) (1990)
Mary Jane Irwin, Robert Michael Owens
A Comparison of Four Two-dimensional Gate Matrix Layout Tools. DAC (1989)
Robert Michael Owens, Mary Jane Irwin
Implementing algorithms for convolution on arrays of adders. ICASSP (1989)
TingTing Hwang, Robert Michael Owens, Mary Jane Irwin
Multi-Level Logic Synthesis Using Communication Complexity. DAC (1989)
Robert Michael Owens, Mary Jane Irwin
Multidimensional algorithms for VLSI processors. ICASSP (1988)
Pao-Po Hou, Robert Michael Owens, Mary Jane Irwin
DECOMPOSER: A Synthesizer for Systolic Systems. DAC (1988)
Mary Jane Irwin, Robert Michael Owens
A comparison of two digit serial VLSI adders. ICCD (1988)
Robert Michael Owens, Mary Jane Irwin
An Overview of the Penn State Design System. DAC (1987)
Robert Michael Owens, Mary Jane Irwin
The Arithmetic Cube. IEEE Trans. Computers 36 (11) (1987)
Mary Jane Irwin, Robert Michael Owens
Digit-Pipelined Arithmetic as Illustrated By the Paste-Up System: A Tutorial. Computer 20 (4) (1987)
Jared A. Beekman, Robert Michael Owens, Mary Jane Irwin
Mesh Arrays and LOGICIAN: A Tool for Their Efficient Generation. DAC (1987)
Poras T. Balsara, Robert Michael Owens
Systolic & semi-systolic digit serial multipliers. IEEE Symposium on Computer Arithmetic (1987)
Mary Jane Irwin, Robert Michael Owens
Digit pipelined processors. J. Supercomput. 1 (1) (1987)
Robert Michael Owens, Joseph F. JáJá
A VLSI chip for the winograd/Prime factor algorithm to compute the discrete Fourier transform. IEEE Trans. Acoust. Speech Signal Process. 34 (4) (1986)
Robert Michael Owens, Joseph F. JáJá
Optimal Algorithms for Mesh-Connected Parallel Processors with Serial Memories. ICPP (1986)
Robert Michael Owens, Mary Jane Irwin
A System for Designing, Simulating, and Testing High Performance VLSI Signal Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5 (3) (1986)
Robert Michael Owens, Joseph F. JáJá
Parallel Sorting with Serial Momories. IEEE Trans. Computers 34 (4) (1985)
Joseph F. JáJá, Robert Michael Owens
VLSI Sorting with Reduced Hardware. IEEE Trans. Computers 33 (7) (1984)
Joseph F. JáJá, Robert Michael Owens
An architecture for a VLSI FFT processor. Integr. 1 (4) (1983)
Mary Jane Irwin, Robert Michael Owens
Fully Digit On-Line Networks. IEEE Trans. Computers 32 (4) (1983)
Robert Michael Owens
Techniques to Reduce the Inherent Limitations of Fully Digit On-Line Arithmetic. IEEE Trans. Computers 32 (4) (1983)

Robert Michael Owens.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Robert Michael Owens