Transistor sizing for low power CMOS circuits.
Manjit BorahRobert Michael OwensMary Jane IrwinPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1996)
Keyphrases
- low power
- power dissipation
- high speed
- cmos technology
- delay insensitive
- power consumption
- logic circuits
- vlsi circuits
- mixed signal
- low cost
- power reduction
- single chip
- digital signal processing
- chip design
- high power
- image sensor
- wireless transmission
- nm technology
- low voltage
- wide dynamic range
- vlsi architecture
- low power consumption
- analog vlsi
- gate array
- real time
- ultra low power
- power management
- floating gate
- video sequences