Mohan Vishwanath

Publication Activity (10 Years)

Years Active: 1991-1998
Publications (10 Years): 0

Publications

Robert Michael Owens, Mohan Vishwanath
A Very Efficient Storage Structure for DWT and IDWT Filters. J. VLSI Signal Process. 19 (3) (1998)
Daniel Greene, Mohan Vishwanath, F. Frances Yao, Tong Zhang
A progressive Ziv-Lempel algorithm for image compression. SEQUENCES (1997)
Navin Chaddha, Mohan Vishwanath
A low power video encoder with power, memory and bandwidth scalability. VLSI Design (1996)
Rajan L. Joshi, Mohan Vishwanath
Improving the performance of hierarchical vector quantization using segmentation. ICIP (3) (1996)
Chaitali Chakrabarti, Mohan Vishwanath, Robert Michael Owens
Architectures for wavelet transforms: A survey. J. VLSI Signal Process. 14 (2) (1996)
Mohan Vishwanath, Robert Michael Owens
A Common Architecture For The DWT and IDWT. ASAP (1996)
Manjit Borah, Chetana Nagendra, Mohan Vishwanath, Robert Michael Owens, Mary Jane Irwin
An optimal time multiplication free algorithm for edge detection on a mesh. J. VLSI Signal Process. 13 (1) (1996)
Chaitali Chakrabarti, Mohan Vishwanath
Efficient realizations of the discrete and continuous wavelet transforms: from single chip implementations to mappings on SIMD array computers. IEEE Trans. Signal Process. 43 (3) (1995)
Chaitali Chakrabarti, Mohan Vishwanath, Robert Michael Owens
A survey of architectures for the discrete and continuous wavelet transforms. ICASSP (1995)
Navin Chaddha, Mohan Vishwanath, Philip A. Chou
Hierarchical Vector Quantization of Perceptually Weighted Block Transforms. Data Compression Conference (1995)
Mohan Vishwanath, Chaitali Chakrabarti
A VLSI architecture for real-time hierarchical encoding/decoding of video using the wavelet transform. ICASSP (2) (1994)
Mohan Vishwanath
Algorithms and architectures for hierarchical compression of video. ASAP (1994)
Mohan Vishwanath
The recursive pyramid algorithm for the discrete wavelet transform. IEEE Trans. Signal Process. 42 (3) (1994)
Mohan Vishwanath, Philip A. Chou
An Efficient Algorithm for Hierarchical Compression of Video. ICIP (3) (1994)
Chetana Nagendra, Manjit Borah, Mohan Vishwanath, Robert Michael Owens, Mary Jane Irwin
Edge detection using fine-grained parallelism in VLSI. ICASSP (1) (1993)
Chen-Mi Wu, Mohan Vishwanath, Robert Michael Owens, Mary Jane Irwin
A new blocked IIR algorithm. ICASSP (3) (1993)
Robert Michael Owens, Thomas P. Kelliher, Mary Jane Irwin, Mohan Vishwanath, Raminder Singh Bajwa, Wen-Lin Yang
The design and implementation of the Arithmetic Cube II, a VLSI signal processing system. IEEE Trans. Very Large Scale Integr. Syst. 1 (4) (1993)
Mohan Vishwanath, Robert Michael Owens, Mary Jane Irwin
Discrete wavelet transforms in VLSI. ASAP (1992)
Mohan Vishwanath, Robert Michael Owens
lower bound for wavelet transforms in VLSI. ICASSP (1992)
Mohan Vishwanath, Robert Michael Owens, Mary Jane Irwin
ECube: An Efficient Architecture for Analyzing Time-Varying Spectra. VLSI Design (1992)
Robert Michael Owens, Mary Jane Irwin, Thomas P. Kelliher, Mohan Vishwanath, Raminder Singh Bajwa
Implementing a family of high performance, micrograined architectures. ASAP (1992)
Mohan Vishwanath, Robert Michael Owens, Mary Jane Irwin
The Arithmetic Cube: error analysis and simulation. ASAP (1991)
Mary Jane Irwin, Robert Michael Owens, Thomas P. Kelliher, Kin-Ki Leung, Mohan Vishwanath
The arithmetic cube II: a second generation VLSI DSP processor. ICASSP (1991)