Chetana Nagendra

Publication Activity (10 Years)

Years Active: 1993-1996
Publications (10 Years): 0

Publications

Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin
Design tradeoffs in high speed multipliers and FIR filters. VLSI Design (1996)
Manjit Borah, Chetana Nagendra, Mohan Vishwanath, Robert Michael Owens, Mary Jane Irwin
An optimal time multiplication free algorithm for edge detection on a mesh. J. VLSI Signal Process. 13 (1) (1996)
Chetana Nagendra, Mary Jane Irwin
Design tradeoffs in CMOS FIR filters. ICASSP (1996)
Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin
Digit pipelined arithmetic on fine-grain array processors. J. VLSI Signal Process. 9 (3) (1995)
Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin
Unifying carry-sum and signed-digital number representations for low power. ISLPD (1995)
Manjit Borah, Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin
The MGAP: A High Performance, User Programmable, Multifunctional Architecture for DS. HICSS (1) (1994)
Chetana Nagendra, Mary Jane Irwin, Robert Michael Owens
Digit pipelined discrete wavelet transform. ICASSP (2) (1994)
Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin
Power-delay characteristics of CMOS adders. IEEE Trans. Very Large Scale Integr. Syst. 2 (3) (1994)
Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin
Digit systolic algorithms for fine-grain architectures. ASAP (1993)
Chetana Nagendra, Manjit Borah, Mohan Vishwanath, Robert Michael Owens, Mary Jane Irwin
Edge detection using fine-grained parallelism in VLSI. ICASSP (1) (1993)