Minimizing power consumption of static CMOS circuits by transistor sizing and input reordering.
Manjit BorahMary Jane IrwinRobert Michael OwensPublished in: VLSI Design (1995)
Keyphrases
- power consumption
- power dissipation
- low power
- cmos technology
- high speed
- power reduction
- power saving
- energy efficiency
- power management
- battery life
- delay insensitive
- energy management
- nm technology
- energy saving
- low power consumption
- single chip
- digital signal processing
- data center
- floating gate
- clock gating
- circuit design
- low cost
- battery powered
- response time