Rama Sangireddy

Publication Activity (10 Years)

Years Active: 2001-2010
Publications (10 Years): 0

Publications

Mangesh K. Kunchamwar, Durga P. Prasad, Pawan Hegde, Poras T. Balsara, Rama Sangireddy
Application Specific Instruction Accelerator for Multistandard Viterbi and Turbo Decoding. ICPP Workshops (2010)
Hui Wang, Rama Sangireddy, Sandeep Baldawa
Optimizing Instruction Scheduling through Combined In-Order and O-O-O Execution in SMT Processors. IEEE Trans. Parallel Distributed Syst. 20 (3) (2009)
Terrell Bennett, Rama Sangireddy
An Optimal Multi-Functional Unit Dynamic Instruction Selection Logic at Submicron Technologies. VLSI Design (2008)
Rama Sangireddy, Jatan P. Shah
Operand-Load-Based Split Pipeline Architecture for High Clock Rate and Commensurable IPC. IEEE Trans. Parallel Distributed Syst. 19 (4) (2008)
Hui Wang, Rama Sangireddy
Streamlining long latency instructions for seamlessly combined out-of-order and in-order execution. Microprocess. Microsystems 32 (7) (2008)
Hui Wang, Sandeep Baldawa, Rama Sangireddy
Dynamic Error Detection for Dependable Cache Coherency in Multicore Architectures. VLSI Design (2008)
Rama Sangireddy
Register port complexity reduction in wide-issue processors with selective instruction execution. Microprocess. Microsystems 31 (1) (2007)
Rama Sangireddy, Prabhu Rajamani
Scalable Reconfigurable Architectures for High-Performance Energy-Efficient Multimedia Processing. Int. J. Comput. Their Appl. 14 (2) (2007)
Jatan P. Shah, Rama Sangireddy
Higher Clock Rate at Comparable IPC Through Reduced Circuit Complexity in Instruction Format Based Pipeline Clustering. ISCAS (2007)
Rama Sangireddy, Arun K. Somani
On-Chip Adaptive Circuits for Fast Media Processing. IEEE Trans. Circuits Syst. II Express Briefs (9) (2006)
Rama Sangireddy, Prabhu Rajamani, Shwetha Gaddam
Performance Optimization with Scalable Reconfigurable Computing Systems. VLSI Design (2006)
Prabhu Rajamani, Jatan P. Shah, Vadhiraj Sankaranarayanan, Rama Sangireddy
High performance and alleviated hot-spot problem in processor frontend with enhanced instruction fetch bandwidth utilization. IPCCC (2006)
Rama Sangireddy
Reducing Rename Logic Complexity for High-Speed and Low-Power Front-End Architectures. IEEE Trans. Computers 55 (6) (2006)
Rama Sangireddy
Instruction Format Based Selective Execution for Register Port Complexity Reduction in High-Performance Processors. ITNG (2006)
Rama Sangireddy
Fast and low-power processor front-end with reduced rename logic circuit complexity. ISCAS (2006)
Rama Sangireddy, Natsuhiko Futamura, Srinivas Aluru, Arun K. Somani
Scalable, memory efficient, high-speed IP lookup algorithms. IEEE/ACM Trans. Netw. 13 (4) (2005)
Rama Sangireddy
Register Organization for Enhanced On-Chip Parallelism. ASAP (2004)
Rama Sangireddy, Arun K. Somani
Exploiting Quiescent States in Register Lifetime. ICCD (2004)
Rama Sangireddy, Huesung Kim, Arun K. Somani
Low-Power High-Performance Reconfigurable Computing Cache Architectures. IEEE Trans. Computers 53 (10) (2004)
Rama Sangireddy, Arun K. Somani
Application-Specific Computing with Adaptive Register File Architectures. ASAP (2003)
Natsuhiko Futamura, Rama Sangireddy, Srinivas Aluru, Arun K. Somani
Scalable, memory efficient, high-speed lookup and update algorithms for IP routing. ICCCN (2003)
Rama Sangireddy, Arun K. Somani
High-speed IP routing with binary decision diagrams based hardware address lookup engine. IEEE J. Sel. Areas Commun. 21 (4) (2003)
Rama Sangireddy, Huesung Kim, Arun K. Somani
Timing Issues of Operating Mode Switch in High Performance Reconfigurable Architectures. HiPC (2003)
Rama Sangireddy, Huesung Kim, Arun K. Somani
Low-Power High-Performance Adaptive Computing Architectures for Multimedia Processing. HiPC (2002)
Rama Sangireddy, Arun K. Somani
Binary decision diagrams for efficient hardware implementation of fast IP routing lookups. ICCCN (2001)