Reducing Rename Logic Complexity for High-Speed and Low-Power Front-End Architectures.
Rama SangireddyPublished in: IEEE Trans. Computers (2006)
Keyphrases
- low power
- high speed
- logic circuits
- low cost
- power consumption
- power reduction
- delay insensitive
- wireless transmission
- digital signal processing
- single chip
- low power consumption
- high power
- computational complexity
- vlsi circuits
- real time
- signal processor
- vlsi architecture
- cmos technology
- frame rate
- computer simulation
- gate array
- mixed signal
- nm technology