Fast and low-power processor front-end with reduced rename logic circuit complexity.
Rama SangireddyPublished in: ISCAS (2006)
Keyphrases
- low power
- logic circuits
- high speed
- gate array
- single chip
- delay insensitive
- power consumption
- low cost
- power dissipation
- power reduction
- chip design
- cmos technology
- logic synthesis
- high power
- digital signal processing
- wireless transmission
- vlsi architecture
- mixed signal
- low power consumption
- vlsi circuits
- real time
- image sensor
- nm technology
- computational complexity