High performance low power array multiplier using temporal tiling.
Shivaling S. Mahant-ShettiPoras T. BalsaraCarl LemondsPublished in: IEEE Trans. Very Large Scale Integr. Syst. (1999)
Keyphrases
- low power
- low power consumption
- signal processor
- high speed
- low cost
- power consumption
- image sensor
- single chip
- high power
- logic circuits
- wireless transmission
- digital signal processing
- signal processing
- vlsi architecture
- real time
- mixed signal
- vlsi circuits
- cmos technology
- focal plane
- hardware and software
- gate array
- power dissipation
- hardware implementation
- motion estimation