Amit Chowdhary

Publication Activity (10 Years)

Years Active: 1994-2006
Publications (10 Years): 0

Publications

Sherief Reda, Amit Chowdhary
Effective linear programming based placement methods. ISPD (2006)
Amit Chowdhary, John P. Hayes
Area-optimal technology mapping for field-programmable gate arrays based on lookup tables. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (7) (2005)
Amit Chowdhary, Karthik Rajagopal, Satish Venkatesan, Tung Cao, Vladimir Tiourin, Yegna Parasuram, Bill Halpin
How accurately can we model timing in a placement engine? DAC (2005)
Karthik Rajagopal, Tal Shaked, Yegna Parasuram, Tung Cao, Amit Chowdhary, Bill Halpin
Timing driven force directed placement with physical net constraints. ISPD (2003)
Sung-Woo Hur, Tung Cao, Karthik Rajagopal, Yegna Parasuram, Amit Chowdhary, Vladimir Tiourin, Bill Halpin
Force directed mongrel with physical net constraints. DAC (2003)
Amit Chowdhary, Rajesh K. Gupta
A Methodology for Synthesis of Data Path Circuitse. IEEE Des. Test Comput. 19 (6) (2002)
Amit Chowdhary, John P. Hayes
General technology mapping for field-programmable gate arrays based on lookup tables. ACM Trans. Design Autom. Electr. Syst. 7 (1) (2002)
Amit Chowdhary, Sudhakar Kale, Phani K. Saripella, Naresh Sehgal, Rajesh K. Gupta
Extraction of functional regularity in datapath circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (9) (1999)
Amit Chowdhary, Sudhakar Kale, Phani K. Saripella, Naresh Sehgal, Rajesh K. Gupta
A general approach for regularity extraction in datapath circuits. ICCAD (1998)
Amit Chowdhary, John P. Hayes
General Modeling and Technology-Mapping Technique for LUT-Based FPGAs. FPGA (1997)
Dinesh Bhatia, Amit Chowdhary
A Multi-Terminal Net Router for Field-Programmable Gate Arrays. VLSI Design 4 (1) (1996)
Amit Chowdhary, John P. Hayes
Technology mapping for field-programmable gate arrays using integer programming. ICCAD (1995)
Amit Chowdhary, Dinesh Bhatia
Detailed Routing of Multi-Terminal Nets in FPGAs. VLSI Design (1994)
Dinesh Bhatia, Amit Chowdhary, Spyros Tragoudas
Mathematical model for routability analysis of FPGAs. Great Lakes Symposium on VLSI (1994)