Naresh Sehgal

Publication Activity (10 Years)

Years Active: 1994-2003
Publications (10 Years): 0

Publications

Bharat Krishna, C. Y. Roger Chen, Naresh Sehgal
A novel ultra-fast heuristic for VLSI CAD steiner trees. ACM Great Lakes Symposium on VLSI (2003)
Bill Halpin, Naresh Sehgal, C. Y. Roger Chen
Detailed Placement with Net Length Constraints. IWSOC (2003)
Bill Halpin, C. Y. Roger Chen, Naresh Sehgal
Timing Driven Placement using Physical Net Constraints. DAC (2001)
Bharat Krishna, C. Y. Roger Chen, Naresh Sehgal
A novel technique for sea of gates global routing. ACM Great Lakes Symposium on VLSI (2000)
Bill Halpin, C. Y. Roger Chen, Naresh Sehgal
A sensitivity based placer for standard cells. ACM Great Lakes Symposium on VLSI (2000)
Bulent Basaran, Kiran Ganesh, Raymond Y. K. Lau, Artour Levin, Miles McCoo, Srinivasan Rangarajan, Naresh Sehgal
GeneSys: A Leaf-Cell Layout Synthesis System for GHz VLSI Designs. VLSI Design (1999)
Amit Chowdhary, Sudhakar Kale, Phani K. Saripella, Naresh Sehgal, Rajesh K. Gupta
Extraction of functional regularity in datapath circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (9) (1999)
Amit Chowdhary, Sudhakar Kale, Phani K. Saripella, Naresh Sehgal, Rajesh K. Gupta
A general approach for regularity extraction in datapath circuits. ICCAD (1998)
Bharat Krishna, C. Y. Roger Chen, Naresh Sehgal
Technique for Planning of Terminal Locations of Leaf Cells in Cell-Based Design with Routing Considerations. VLSI Design (1998)
Deo Singh, Jan M. Rabaey, Massoud Pedram, Francky Catthoor, Suresh Rajgopal, Naresh Sehgal, Thomas J. Mozdzen
Power conscious CAD tools and methodologies: a perspective. Proc. IEEE 83 (4) (1995)
Naresh Sehgal, C. Y. Roger Chen, John M. Acken
A gridless multi-layer area router. Great Lakes Symposium on VLSI (1994)
Naresh Sehgal, C. Y. Roger Chen, John M. Acken
An object-oriented cell library manager. ICCAD (1994)