Shankar Balachandran

Publication Activity (10 Years)

Years Active: 2001-2022
Publications (10 Years): 9

Top Topics

Multicore Processors

Top Venues

Publications

Rahul Bera, Konstantinos Kanellopoulos, Shankar Balachandran, David Novo, Ataberk Olgun, Mohammad Sadrosadati, Onur Mutlu
Hermes: Accelerating Long-Latency Load Requests via Perceptron-Based Off-Chip Load Prediction. MICRO (2022)
Rahul Bera, Konstantinos Kanellopoulos, Shankar Balachandran, David Novo, Ataberk Olgun, Mohammad Sadrosadati, Onur Mutlu
Hermes: Accelerating Long-Latency Load Requests via Perceptron-Based Off-Chip Load Prediction. CoRR (2022)
Anant V. Nori, Rahul Bera, Shankar Balachandran, Joydeep Rakshit, Om Ji Omer, Avishaii Abuhatzera, Belliappa Kuttanna, Sreenivas Subramoney
REDUCT: Keep it Close, Keep it Cool! : Efficient Scaling of DNN Inference on Multi-core CPUs with Near-Cache Compute. ISCA (2021)
Antara Ganguly, Shankar Balachandran, Anant V. Nori, Virendra Singh, Sreenivas Subramoney
Characterization of Data Generating Neural Network Applications on x86 CPU Architecture. ISPASS (2020)
Anant V. Nori, Rahul Bera, Shankar Balachandran, Joydeep Rakshit, Om Ji Omer, Avishaii Abuhatzera, Belliappa Kuttanna, Sreenivas Subramoney
Proximu: Efficiently Scaling DNN Inference in Multi-core CPUs through Near-Cache Compute. CoRR (2020)
Jyothi Krishna V. S, Shankar Balachandran
Compiler Enhanced Scheduling for OpenMP for Heterogeneous Multiprocessors. CoRR (2018)
Jyothi Krishna Viswakaran Sreelatha, Shankar Balachandran, Rupesh Nasre
CHOAMP: Cost Based Hardware Optimization for Asymmetric Multicore Processors. IEEE Trans. Multi Scale Comput. Syst. 4 (2) (2018)
Shankar Balachandran, Sajin Koroth
Subclasses of Baxter Permutations Based on Pattern Avoidance. CSR (2016)
Biswabandan Panda, Shankar Balachandran
Expert Prefetch Prediction: An Expert Predicting the Usefulness of Hardware Prefetchers. IEEE Comput. Archit. Lett. 15 (1) (2016)
Biswabandan Panda, Shankar Balachandran
CAFFEINE: A Utility-Driven Prefetcher Aggressiveness Engine for Multicores. ACM Trans. Archit. Code Optim. 12 (3) (2015)
Aditya Pratapa, Shankar Balachandran, Karthik Raman
Fast-SL: an efficient algorithm to identify synthetic lethal sets in metabolic networks. Bioinform. 31 (20) (2015)
Milan Patnaik, Chidhambaranathan Rajamanikkam, Chirag Garg, Arnab Roy, V. R. Devanathan, Shankar Balachandran, V. Kamakoti
ProWATCh: A Proactive Cross-Layer Workload-Aware Temperature Management Framework for Low-Power Chip Multi-Processors. ACM J. Emerg. Technol. Comput. Syst. 12 (3) (2015)
Parth Lathigara, Shankar Balachandran, Virendra Singh
Application behavior aware re-reference interval prediction for shared LLC. ICCD (2015)
B. N. Bhramar Ray, Shankar Balachandran
A Recursive Model for Smooth Approximation to Wirelength and Its Impact on Analytical Placement. VLSI Design (2015)
Adithyalal P. M, Shankar Balachandran, Virendra Singh
A Soft Error Resilient Low Leakage SRAM Cell Design. ATS (2015)
Nihar Rathod, Shankar Balachandran, Neel Gala
CAERUS: an effective arbitration and ejection policy for routing in an unidirectional torus. INA-OCMC@HiPEAC (2014)
Biswabandan Panda, Shankar Balachandran
XStream: cross-core spatial streaming based MLC prefetchers for parallel applications in CMPs. PACT (2014)
Biswabandan Panda, Shankar Balachandran
Introducing Thread Criticality awareness in Prefetcher Aggressiveness Control. DATE (2014)
Satya Trinadh, Seetal Potluri, Shankar Balachandran, Ch. Sobhan Babu, V. Kamakoti
-Filling Algorithm for Peak Capture Power Reduction in Scan Tests. J. Low Power Electron. 10 (1) (2014)
B. N. Bhramar Ray, Shankar Balachandran
An efficient wirelength model for analytical placement. DATE (2013)
Biswabandan Panda, Shankar Balachandran
TCPT - Thread criticality-driven prefetcher throttling. PACT (2013)
Seetal Potluri, Satya Trinadh Adireddy, Chidhambaranathan Rajamanikkam, Shankar Balachandran
LPScan: An algorithm for supply scaling and switching activity minimization during test. ICCD (2013)
Madhur Amilkanthwar, Shankar Balachandran
CUPL: a compile-time uncoalesced memory access pattern locator for CUDA. ICS (2013)
Ankit Kagliwal, Shankar Balachandran
Measuring Area-Complexity Using Boolean Difference. VLSI Design (2013)
Biswabandan Panda, Shankar Balachandran
CSHARP: Coherence and SHaring Aware Cache Replacement Policies for Parallel Applications. SBAC-PAD (2012)
Sharmistha, Madhur Amilkanthwar, Shankar Balachandran
Augmentation of Programs with CUDA Streams. ISPA (2012)
Biswabandan Panda, Shankar Balachandran
Hardware prefetchers for emerging parallel applications. PACT (2012)
Ankit Kagliwal, Shankar Balachandran
Set-Cover Heuristics for Two-Level Logic Minimization. VLSI Design (2012)
Ashok Gautham, Kunal Korgaonkar, Patanjali SLPSK, Shankar Balachandran, Kamakoti Veezhinathan
The Implications of Shared Data Synchronization Techniques on Multi-Core Energy Efficiency. HotPower (2012)
Nitin Chandrachoodan, Shankar Balachandran
24th "IEEE International Conference on VLSI Design" Chennai, India, 2-7 January 2011. J. Low Power Electron. 7 (4) (2011)
Shankar Balachandran, Sajin Koroth
A Study on Hierarchical Floorplans of Order k CoRR (2011)
Shankar Balachandran, Sajin Koroth
A study on the number of Hierarchical Rectangular Partitions of Order k CoRR (2011)
B. N. Bhramar Ray, Shankar Balachandran
A New Wirelength Model for Analytical Placement. ISVLSI (2011)
Shankar Balachandran, Dinesh Bhatia
Timing Aware Interconnect Prediction Models for FPGAs. FPL (2005)
Shankar Balachandran, Dinesh Bhatia
A priori wirelength and interconnect estimation based on circuit characteristic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (7) (2005)
PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia
On metrics for comparing interconnect estimation methods for FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 12 (4) (2004)
Shankar Balachandran, Dinesh Bhatia
A-priori wirelength and interconnect estimation based on circuit characteristics. SLIP (2003)
PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia
On metrics for comparing routability estimation methods for FPGAs. DAC (2002)
PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia
Rapid and Reliable Routability Estimation for FPGAs. FPL (2002)
Shankar Balachandran, PariVallal Kannan, Dinesh Bhatia
On Routing Demand and Congestion Estimation for FPGAs. VLSI Design (2002)
PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia
fGREP - Fast Generic Routing Demand Estimation for Placed FPGA Circuits. FPL (2001)