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Clock power minimization using structured latch templates and decision tree induction.
Samuel I. Ward
Natarajan Viswanathan
Nancy Y. Zhou
Cliff C. N. Sze
Zhuo Li
Charles J. Alpert
David Z. Pan
Published in:
ICCAD (2013)
Keyphrases
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decision tree induction
power consumption
decision trees
low power
attribute selection
pruning methods
data mining methods
cross validation
power reduction
duty cycle
preprocessing
learning algorithm
power dissipation
real world
naive bayes
nearest neighbor
genetic algorithm
data sets