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High-speed interconnect and packaging design of the IBM System z9 processor cage.

Hubert HarrerDaniel M. DrepsThomas-Michael WinkelWolfgang ScholzBao G. TruongAndreas HuberTingdong ZhouKenneth L. ChristianGary F. Goth
Published in: IBM J. Res. Dev. (2007)
Keyphrases
  • high speed
  • low power
  • single chip
  • real time
  • design process
  • case study
  • control system
  • building blocks
  • operating system
  • engineering design
  • gate array
  • neural network
  • computer aided
  • high speed networks