SWEC: a Step Wise Equivalent Conductance timing simulator for CMOS VLSI circuits.

Shen Lin Malgorzata Marek-Sadowska Ernest S. Kuh

Published in: EURO-DAC (1991)

Keyphrases

vlsi circuits
step wise
low power
low cost
simulation model
mixed signal
image processing
power consumption
case study
pattern recognition
multi channel