A hardware/software partitioning algorithm for SIMD processor cores.
Koichi TachikakeNozomu TogawaYuichiro MiyaokaJinku ChoiMasao YanagisawaTatsuo OhtsukiPublished in: ASP-DAC (2003)
Keyphrases
- partitioning algorithm
- hardware software
- multi core processors
- parallel programming
- parallel algorithm
- parallel architectures
- massively parallel
- parallel processing
- hw sw
- graph partitioning
- computing resources
- level parallelism
- hardware design
- single instruction multiple data
- gene expression programming
- field programmable gate array
- hardware and software
- parallel implementation
- fine grained
- parallel computing
- graph cuts
- image processing
- computer vision