A thread partitioning algorithm in low power high-level synthesis.
Jumpei UchidaNozomu TogawaMasao YanagisawaTatsuo OhtsukiPublished in: ASP-DAC (2004)
Keyphrases
- partitioning algorithm
- low power
- high level synthesis
- power consumption
- low cost
- high speed
- parallel architecture
- graph partitioning
- single chip
- vlsi circuits
- logic circuits
- vlsi architecture
- low power consumption
- cmos technology
- design space exploration
- mixed signal
- energy efficiency
- power reduction
- computing systems
- image sensor
- real time
- pattern recognition