Masayoshi Tachibana

Publication Activity (10 Years)

Years Active: 1986-2018
Publications (10 Years): 3

Top Topics

Phase Difference

Analog Circuits

Random Number Generator

Top Venues

IEICE Electron. Express

Publications

Chatchai Wannaboon, Nattagit Jiteurtragool, Wimol San-Um, Masayoshi Tachibana
Phase difference analysis technique for parametric faults BIST in CMOS analog circuits. IEICE Electron. Express 15 (9) (2018)
Nattagit Jiteurtragool, Masayoshi Tachibana, Wimol San-Um
Robustification of a One-Dimensional Generic Sigmoidal Chaotic Map with Application of True Random Bit Generation. Entropy 20 (2) (2018)
Patinya Ketthong, Wimol San-Um, Banlue Srisuchinwong, Masayoshi Tachibana
A simple current-reversible chaotic jerk circuit using inherent tanh(x) of an opamp. IEICE Electron. Express 14 (17) (2017)
Nattagit Jiteurtragool, Chatchai Wannaboon, Masayoshi Tachibana
True Random Number Generator based on compact chaotic oscillator. ISCIT (2015)
Chatchai Wannaboon, Masayoshi Tachibana
An autonomous chaotic oscillator based on hyperbolic tangent nonlinearity. ISCIT (2015)
Jun Yuan, Masayoshi Tachibana
A resistance matching based self-testable current-mode R-2R digital-to-analog converter. IEICE Electron. Express 10 (23) (2013)
Jun Yuan, Masayoshi Tachibana
A common-mode BIST technique for fully-differential sample-and-hold circuits. IEICE Electron. Express 9 (13) (2012)
Jun Yuan, Masayoshi Tachibana
A BIST scheme for operational amplifier by checking the stable output of transient response. ECCTD (2011)
Wimol San-Um, Masayoshi Tachibana
A low-jitter supply-regulated charge pump phase-locked loop with built-in test and calibration. ISCAS (2010)
Wimol San-Um, Masayoshi Tachibana
A Fault Signature Characterization Based Analog Circuit Testing Scheme and the Extension of IEEE 1149.4 Standard. IEICE Trans. Inf. Syst. (1) (2010)
Wimol San-Um, Masayoshi Tachibana
Simultaneous impulse stimulation and response sampling technique for built-in self test of linear analog integrated circuits. SBCCI (2009)
Masayoshi Tachibana, Yoshihisa Kondo, Yasuo Yamada, Masafumi Takahashi, Haruyuki Tago
High performance I/O processors for real-time pulse handling. ICCD (1989)
Kei Suzuki, Yusuke Matsunaga, Masayoshi Tachibana, Tatsuo Ohtsuki
A Hardware Maze Router with Application to Interactive Rip-Up and Reroute. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 5 (4) (1986)