A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions.
Nozomu TogawaKoichi TachikakeYuichiro MiyaokaMasao YanagisawaTatsuo OhtsukiPublished in: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2003)
Keyphrases
- hardware software
- multi core processors
- partitioning algorithm
- parallel programming
- processor core
- parallel algorithm
- parallel architectures
- hardware and software
- hw sw
- parallel processing
- gene expression programming
- graph partitioning
- massively parallel
- computing resources
- hardware design
- operating system
- real time
- embedded systems
- computer vision
- design methodology
- parallel implementation
- efficient implementation
- low cost
- level parallelism