Instruction set and functional unit synthesis for SIMD processor cores.
Nozomu TogawaKoichi TachikakeYuichiro MiyaokaMasao YanagisawaTatsuo OhtsukiPublished in: ASP-DAC (2004)
Keyphrases
- instruction set
- level parallelism
- floating point
- computer architecture
- parallel processing
- application specific
- embedded systems
- ibm power processor
- parallel architectures
- massively parallel
- low cost
- parallel algorithm
- computer systems
- memory subsystem
- floating point unit
- parallel implementation
- shared memory
- distributed systems
- database
- instruction set architecture