A low-power soft error tolerant latch scheme.

Saki Tajima Youhua Shi Nozomu Togawa Masao Yanagisawa

Published in: ASICON (2015)

Keyphrases

low power
error tolerant
power consumption
low cost
high speed
graph matching
digital signal processing
low power consumption
power reduction
image sensor
logic circuits
real time
cmos technology
mixed signal
subgraph isomorphism
wireless sensor networks
pairwise
image processing