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A Bit-Segmented Adder Chain based Symmetric Transpose Two-Block FIR Design for High-Speed Signal Processing.
Jinghao Ye
Masao Yanagisawa
Youhua Shi
Published in:
APCCAS (2019)
Keyphrases
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hardware implementation
signal processing
high speed
filter bank
digital signal processing
pattern recognition
fourier transform
engineering design
user interface
design principles
neural network
knowledge based systems
design process
multiresolution
software architecture
low power
filter design