Soft error tolerant latch designs with low power consumption (invited paper).

Saki Tajima Nozomu Togawa Masao Yanagisawa Youhua Shi

Published in: ASICON (2017)

Keyphrases

error tolerant
invited paper
low power consumption
low power
power consumption
low cost
high speed
graph matching
single chip
real time
application specific
association patterns
subgraph isomorphism
lecture notes
matching algorithm
data sources
pattern recognition