Minor-embedding heuristics for large-scale annealing processors with sparse hardware graphs of up to 102, 400 nodes.
Yuya SugieYuki YoshidaNormann MertigTakashi TakemotoHiroshi TeramotoAtsuyoshi NakamuraIchigaku TakigawaShin-ichi MinatoMasanao YamaokaTamiki KomatsuzakiPublished in: Soft Comput. (2021)
Keyphrases
- massive graphs
- directed graph
- graph structure
- nodes of a graph
- processing elements
- graph structures
- list scheduling
- graph embedding
- undirected graph
- high end
- real world networks
- real time
- processing units
- random graphs
- embedded processors
- densely connected
- low cost
- multi core processors
- parallel algorithm
- parallel processing
- parallel architecture
- simulated annealing
- weighted graph
- reachability queries
- adjacency matrix
- small world
- scheduling problem
- parallel processors
- hardware and software
- parallel architectures
- fully connected
- random walk
- attributed graphs
- hardware implementation
- finding the shortest path
- graph matching
- search algorithm
- load balance
- multithreading
- social networks
- high dimensional
- connected graphs
- complex networks
- spanning tree
- edge weights
- spectral embedding
- vector space
- network structure
- minimum cost
- planar graphs
- instruction set
- parallel computation
- graph clustering
- dimensionality reduction
- hardware architecture
- computer systems
- computing systems
- community detection
- sparse representation
- semi supervised