A 1.3-Mbit Annealing System Composed of Fully-Synchronized 9-board x 9-chip x 16-kbit Annealing Processor Chips for Large-Scale Combinatorial Optimization Problems.
Kasho YamamotoTakashi TakemotoChihiro YoshimuraMayumi MashimoMasanao YamaokaPublished in: A-SSCC (2021)
Keyphrases
- combinatorial optimization problems
- simulated annealing
- high speed
- metaheuristic
- combinatorial optimization
- discrete optimization
- optimization problems
- knapsack problem
- chip design
- ant colony optimization
- single chip
- high density
- job shop scheduling
- job shop scheduling problem
- evolutionary algorithm
- ibm zenterprise
- traveling salesman problem
- shortest path problem
- tabu search
- high end
- functional units
- minmax regret
- low power
- vehicle routing problem
- parallel processing
- ibm power processor
- multichip module
- genetic algorithm
- interval data
- min cost
- continuous optimization problems
- computer architecture
- benchmark problems
- functional verification
- search algorithm
- optimal solution