24.3 20k-spin Ising chip for combinational optimization problem with CMOS annealing.
Masanao YamaokaChihiro YoshimuraMasato HayashiTakuya OkuyamaHidetaka AokiHiroyuki MizunoPublished in: ISSCC (2015)
Keyphrases
- analog vlsi
- combinational optimization
- cmos image sensor
- high speed
- circuit design
- minimal cost
- low cost
- single chip
- cmos technology
- chip design
- image sensor
- np hard
- focal plane
- low power
- random access memory
- simulated annealing
- markov random field
- power dissipation
- dynamic range
- ant colony optimisation
- nm technology
- ultra low power
- infrared
- physical design
- scheduling problem
- power consumption
- mixed signal
- genetic algorithm
- metal oxide semiconductor
- silicon on insulator
- lower bound
- objective function
- analog to digital converter
- optimal solution
- genetic programming
- special case