0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell.
Kenichi OsadaJinuk Luke ShinMasood KhanYude LiouKarl WangKenichi ShojiKenichi KurodaShuji IkedaKoichiro IshibashiPublished in: IEEE J. Solid State Circuits (2001)