An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM.
Kiichi NiitsuYasuhisa ShimazakiYasufumi SugimoriYoshinori KohamaKazutaka KasugaItaru NonomuraMakoto SaenShigenobu KomatsuKenichi OsadaNaohiko IrieToshihiro HattoriAtsushi HasegawaTadahiro KurodaPublished in: ISSCC (2009)
Keyphrases
- cmos technology
- nm technology
- power consumption
- low power
- silicon on insulator
- random access memory
- parallel processing
- metal oxide semiconductor
- high speed
- low voltage
- dynamic random access memory
- embedded dram
- single chip
- ibm power processor
- low cost
- power dissipation
- leakage current
- image sensor
- analog vlsi
- design considerations
- knowledge representation
- power management
- circuit design
- chip design
- cmos image sensor
- integrated circuit
- video camera
- inductive learning