Toshinobu Shinbo

Publication Activity (10 Years)

Years Active: 1995-1996
Publications (10 Years): 0

Publications

Hiroyuki Mizuno, Nozomu Matsuzaki, Kenichi Osada, Toshinobu Shinbo, Nagatoshi Ohki, Hiroshi Ishida, Koichiro Ishibashi, Tokuo Kure
A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators. IEEE J. Solid State Circuits 31 (11) (1996)
Norio Ohkubo, Makoto Suzuki, Toshinobu Shinbo, Toshiaki Yamanaka, Akihiro Shimizu, Katsuro Sasaki, Yoshinobu Nakagome
A 4.4 ns CMOS 54⨉54-b multiplier using pass-transistor multiplexer. IEEE J. Solid State Circuits 30 (3) (1995)