Katsuro Sasaki

Publication Activity (10 Years)

Years Active: 1994-1997
Publications (10 Years): 0

Publications

Raminder Singh Bajwa, Mitsuru Hiraki, Hirotsugu Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Koichi Seki, Katsuro Sasaki
Instruction buffering to reduce power in processors for signal processing. IEEE Trans. Very Large Scale Integr. Syst. 5 (4) (1997)
Mitsuru Hiraki, Raminder Singh Bajwa, Hirotsugu Kojima, Douglas J. Gorny, Ken-ichi Nitta, Avadhani Shridhar, Katsuro Sasaki, Koichi Seki
Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer. ISLPED (1996)
Suguru Tachibana, Hisayuki Higuchi, Koichi Takasugi, Katsuro Sasaki, Toshiaki Yamanaka, Yoshinobu Nakagome
A 2.6-ns wave-pipelined CMOS SRAM with dual-sensing-latch circuits. IEEE J. Solid State Circuits 30 (4) (1995)
Norio Ohkubo, Makoto Suzuki, Toshinobu Shinbo, Toshiaki Yamanaka, Akihiro Shimizu, Katsuro Sasaki, Yoshinobu Nakagome
A 4.4 ns CMOS 54⨉54-b multiplier using pass-transistor multiplexer. IEEE J. Solid State Circuits 30 (3) (1995)
Hirotsugu Kojima, Satoshi Tanaka, Katsuro Sasaki
Half-swing clocking scheme for 75% power saving in clocking circuitry. IEEE J. Solid State Circuits 30 (4) (1995)
Kiyoo Itoh, Katsuro Sasaki, Yoshinobu Nakagome
Trends in low-power RAM circuit technologies. Proc. IEEE 83 (4) (1995)
Koichiro Ishibashi, Kunihiro Komiyaji, Sadayuki Morita, Toshiro Aoto, Shuji Ikeda, Kyoichiro Asayama, Atsuyosi Koike, Toshiaki Yamanaka, Naotaka Hashimoto, Haruhito Iida, Fumio Kojima, Koichi Motohashi, Katsuro Sasaki
A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layout sense amplifiers. IEEE J. Solid State Circuits 29 (4) (1994)